STM32H7 Series  

STM32H7 series of high-performance MCUs with ARM® Cortex®-M7 core
Taking advantage of an L1 cache, STM32H7 devices deliver the maximum theoretical performance of the Cortex-M7 core, regardless if code is executed from embedded Flash or external memory: 2020 CoreMark /856 DMIPS at 400 MHz fCPU.
Smart architecture with new generation of peripherals set
The STM32H7 series unleashes the Cortex-M7 core:
AXI and multi-AHB bus matrixes for interconnecting core, peripherals and memories
16 Kbytes +16 Kbytes of I-cache and D-cache
Up to 2 Mbytes of embedded dual-bank Flash memory, with ECC and Read-While-Write capability
A high-speed master direct memory access (MDMA) controller, two dual-port DMAs with FIFO and request router capabilities for optimal peripheral management, and one additional DMA
Chrom-ART acceleration for efficient 2D image copy and double-precision FPU are also part of the acceleration features available in the device
Peripheral speed independent from CPU speed (dual-clock support) allowing system clock changes without any impact on peripheral operations
Even more peripherals, such as four serial audio interfaces (SAI) with SPDIF output support, three full-duplex I²S interfaces, a SPDIF input interface supporting four inputs, two USB OTG with dedicated power supply and Dual-mode Quad-SPI interface, two FD-CAN controllers, a high-resolution timer, a TFT-LCD controller, a JPEG codec, two SDIO interfaces and many other analog peripherals including three fast 16-bit ADCs, two comparators and two operational amplifiers.
1 Mbyte of SRAM with a scattered architecture:
192 Kbytes of TCM RAM (including 64 Kbytes of ITCM RAM and 128 Kbytes of DTCM RAM for time-critical routines and data), 512 Kbytes, 288 Kbytes and 64 Kbytes of user SRAM, and 4 Kbytes of SRAM in backup domain to keep data in the lowest power modes
Security
Authenticate and protect your software IP while performing initial programming in production or firmware upgrades in the field (Available in 2018).
Power efficiency
The multi-power domains architecture allows the different power domains to be set in low-power mode to optimize the power efficiency. In addition to the main regulator featuring voltage scaling to supply the core in different voltage ranges during Run and Stop modes, the device also embeds a USB regulator to supply the embedded physical layer (PHY) and a backup regulator.
263 µ/MHz typical @VDD = 3.3 V and 25 °C  in Run mode (peripherals off)
4 µA in Standby mode (low-power mode)
Compatibility
Cortex-M7 is backwards compatible with the Cortex-M4 instruction set
STM32H7 series is pin-to-pin compatible with the STM32F7 series for common packages, and compatible with the STM32F4 series for most of the common packages *
* Note: see datasheet for the specific case of 100-pin packages

 
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STM32H7x3  

The STM32H743/753 lines offer the performance of the Cortex-M7 core (with double-precision floating point unit) running up to 400 MHz while reaching 2 times better dynamic power consumption (Run mode) versus the STM32F7 lines.
Performance
At 400 MHz fCPU, the STM32H743/753 lines deliver 2020 CoreMark /856 DMIPS performance executing from Flash memory, with 0-wait states thanks to its L1 cache. The DSP instructions and the double-precision FPU enlarge the range of addressable applications. External memory can be used with no performance penalty thanks to the L1 cache (16 Kbytes +16 Kbytes of I-cache and D-cache).
Security
Authenticate and protect your software IP while performing initial programming or firmware upgrades in the field*
*Available in 2018
Power efficiency:
The multi-power domains architecture allows the different power domains to be set in low-power mode to optimize the power efficiency. In addition to the main regulator featuring voltage scaling to supply the core in different voltage ranges during Run and Stop modes, the device also embeds a USB regulator to supply the embedded physical layer (PHY) and a backup regulator.
263 µ/MHz typical @VDD = 3.3 V and 25 °C  in Run mode (peripherals off)
4 µA in Standby mode (low-power mode)
Graphics
The new LCD-TFT controller interface with dual-layer support takes advantage of the Chrom‑ART Accelerator™. This graphics accelerator creates content twice as fast as the core alone. As well as efficient 2-D raw data copy, additional functions are supported by the Chrom-ART Accelerator such as image format conversion or image blending (image mixing with some transparency). As a result, the Chrom-ART Accelerator boosts graphics content creation and saves the processing bandwidth of the MCU core for the rest of the application. In addition, the STM32H743/753 lines embed a JPEG hardware accelerator for fast JPEG encoding and decoding, off-loading the CPU which remains available for other tasks.
Integration
Audio: Two dedicated audio PLLs, three full-duplex I²S interfaces, a new serial audio interface (SAI) supporting time-division multiplex (TDM) mode and a DFSDM (Digital filters for sigma-delta modulators or MEMS microphone).
Up to 35 communication interfaces including four USARTs in addition to four UARTs running at up to 12.5 Mbit/s, one low-power UART, six SPIs running at up to 100 Mbit/s, four I²C interfaces running at up to 1 MHz with a new optional digital filter capability, two FD-CAN, two SDIO, USB 2.0 full-speed device/host/OTG controller with an on-chip PHY and a USB 2.0 high-speed/full-speed device/host/OTG controller, on-chip full-speed PHY and ULPI, Ethernet MAC, SPDIF-IN, HDMI-CEC, camera interface, single wire protocol interface and MDIO slave.
Analog: Two 12-bit DACs, three fast ADCs reaching 16-bit maximum resolution (3.6 Msamples/s), 22 16- and 32-bit timers running at up to 400 MHz on the 16-bit high-resolution timer. Easily extendable memory range using the flexible memory controller with a 32-bit parallel interface, and supporting Compact Flash, SRAM, PSRAM, NOR, NAND and SDRAM memories or using the Dual-mode Quad-SPI to allow code execution from external serial Flash memory. An analog true random number generator.
The STM32H7x3 line provides from 1 to 2 Mbytes of Flash memory, 1 Mbyte of SRAM with a scattered architecture: 192 Kbytes of TCM RAM (including 64 Kbytes of ITCM RAM and 128 Kbytes of DTCM RAM for time-critical routines and data), 512 Kbytes, 288 Kbytes and 64 Kbytes of user SRAM, and 4 Kbytes of SRAM in backup domain to keep data in the lowest power modes and 100- to 240-pin packages in BGA and LQFP profiles.
The STM32H753 integrates a crypto/hash processor providing hardware acceleration for AES-128, -192 and -256 encryption, with support for GCM and CCM, Triple DES, and hash (MD5, SHA-1 and SHA-2) algorithms.
  
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